Hybrid Parallel Counters — Domino and Threshold Logic

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	Similar Articles Articles by Troy D. Townsend Articles by Peter Celinski Articles by Said F. Al-Sarawi Articles by Michael J. Liebelt

IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04)

Hybrid Parallel Counters — Domino and Threshold Logic (PDF)

Lafayette, Louisiana

February 19-February 20

ISBN: 0-7695-2097-9

	ASCII Text	x
	Troy D. Townsend, Peter Celinski, Said F. Al-Sarawi, Michael J. Liebelt, "Hybrid Parallel Counters — Domino and Threshold Logic," VLSI, IEEE Computer Society Annual Symposium on, pp. 275, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004.

	BibTex	x
	@article{ 10.1109/ISVLSI.2004.1339555, author = {Troy D. Townsend and Peter Celinski and Said F. Al-Sarawi and Michael J. Liebelt}, title = {Hybrid Parallel Counters — Domino and Threshold Logic}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2097-9}, pages = {275}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339555}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Hybrid Parallel Counters — Domino and Threshold Logic SN - 0-7695-2097-9 SP EP A1 - Troy D. Townsend, A1 - Peter Celinski, A1 - Said F. Al-Sarawi, A1 - Michael J. Liebelt, PY - 2004 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Troy D. Townsend, University of Adelaide

Peter Celinski, University of Adelaide

Said F. Al-Sarawi, University of Adelaide

Michael J. Liebelt, University of Adelaide

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339555

Parallel counters are the building blocks of partial product reduction tree (PPRT) circuits, which are required for high-performance multiplication. In this paper we will implement novel counters using a hybrid of domino and threshold logic. A test 64 ? 64 PPRT using these counters was found to reduce latency by 39% and device count by 38% compared to the domino logic equivalent.

Citation:

Troy D. Townsend, Peter Celinski, Said F. Al-Sarawi, Michael J. Liebelt, "Hybrid Parallel Counters — Domino and Threshold Logic," isvlsi, pp.275, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004

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