Recently, there have been several efforts to develop compilers that synthesize applications written in high-level languages such as C into hardware. Streaming applications form an important class of systems that need to be mapped onto hardware. In this paper we present the modeling of stream and frame based applications in C and extend a behavioral synthesis tool framework to synthesize RTL models from streaming system descriptions in C. Individual C functions get synthesized onto individual IP blocks in the synthesis framework. We describe how the behavioral synthesis tool automatically infers ports and generates the required handshaking signals for interfacing the IP blocks in the system. We describe a system level approach for interfacing synthesized IP blocks. Results of the system level synthesis and simulation are reported for Xilinx VirtexII FPGAs for single IP systems for streaming data and frame-based data, and for multiple IP systems having streaming and frame-based data.