A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture

I
ISVLSI
2004
IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04)
Abstract - A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture

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IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04)

A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture (PDF)

Lafayette, Louisiana

February 19-February 20

ISBN: 0-7695-2097-9

	ASCII Text	x
	Peter Zipf, Claude Stötzler, Manfred Glesner, "A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture," VLSI, IEEE Computer Society Annual Symposium on, pp. 266, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004.

	BibTex	x
	@article{ 10.1109/ISVLSI.2004.1339551, author = {Peter Zipf and Claude Stötzler and Manfred Glesner}, title = {A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2097-9}, pages = {266}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339551}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture SN - 0-7695-2097-9 SP EP A1 - Peter Zipf, A1 - Claude Stötzler, A1 - Manfred Glesner, PY - 2004 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Peter Zipf, Darmstadt University of Technology

Claude Stötzler, Darmstadt University of Technology

Manfred Glesner, Darmstadt University of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339551

We present a con.gurable FSM where all units relevant for control and transition logic are configurable while the basic structural components like state registers are built of fixed logic. Implemented as part of an ASIC, FSMs are efficient and fast, but inflexible. When realized using FPGA hardware, they are very flexible but inefficient in terms of area and speed. We describe the architecture of a combined approach faster and smaller than an FPGA implementation while providing full programmability.

Citation:

Peter Zipf, Claude Stötzler, Manfred Glesner, "A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture," isvlsi, pp.266, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004

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