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IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04)
Multioperand Decimal Addition
Lafayette, Louisiana
February 19-February 20
ISBN: 0-7695-2097-9
Robert D. Kenney, University of Wisconsin-Madison
Michael J. Schulte, University of Wisconsin-Madison
This paper introduces four techniques for performing fast decimal addition on multiple binary coded decimal (BCD) operands. Three of the techniques speculate BCD correction values and use chaining to correct intermediate results. The first speculates over one addition. The second speculates over two additions. The third employs multiple instances of the second technique in parallel and then merges the results. The fourth technique uses a binary carry-save adder tree and produces a binary sum. Combinational logic is then used to correct the sum and determine the carry into the next digit. Multioperand adder designs are constructed and synthesized for four to sixteen input operands. Analyses are performed on the synthesis results and the merits of each technique are discussed. Finally, these techniques are compared to previous attempts made at speeding up decimal addition.
Citation:
Robert D. Kenney, Michael J. Schulte, "Multioperand Decimal Addition," isvlsi, pp.251, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004
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