Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA

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IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04)

Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA (PDF)

Lafayette, Louisiana

February 19-February 20

ISBN: 0-7695-2097-9

	ASCII Text	x
	Sophie Bouchoux, El-Bay Bourennane, Johel Miteran, Michel Paindavoine, "Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA," VLSI, IEEE Computer Society Annual Symposium on, pp. 237, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004.

	BibTex	x
	@article{ 10.1109/ISVLSI.2004.1339540, author = {Sophie Bouchoux and El-Bay Bourennane and Johel Miteran and Michel Paindavoine}, title = {Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2097-9}, pages = {237}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339540}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA SN - 0-7695-2097-9 SP EP A1 - Sophie Bouchoux, A1 - El-Bay Bourennane, A1 - Johel Miteran, A1 - Michel Paindavoine, PY - 2004 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Sophie Bouchoux, LE2I

El-Bay Bourennane, LE2I

Johel Miteran, LE2I

Michel Paindavoine, LE2I

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339540

This paper is about the implementation of a part of the JPEG2000 algorithm (MQ-Decoder and arithmetic decoder) in a FPGA by using dynamic reconfiguration. The implementation is done on an architecture named ARDOISE, created to study fine grain dynamic reconfiguration of FPGAs.

Citation:

Sophie Bouchoux, El-Bay Bourennane, Johel Miteran, Michel Paindavoine, "Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA," isvlsi, pp.237, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004

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