IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04) 64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logic Lafayette, Louisiana February 19-February 20 ISBN: 0-7695-2097-9
A 64-bit low threshold voltage conditional carry adder using complementary pass-transistor logic for low-voltage and high-speed applications was presented. The improved conditional sum addition rule can reduce the number of internal nodes and multiplexers in the adder design. And reducing the threshold voltage increases the speed of operation. Thus, a low threshold voltage design is favorable for implementing low-voltage, high-speed arithmetic systems. The performances of such circuit are compared with that of normal and zero threshold voltage schemes; the proposed circuit gets the lowest power-delay product and energy-delay product from 1.0V to 2.5V. The circuit is demonstrated to balance between power consumption and performance effectively.
Index Terms:
CPL, conditional sum adder, low-threshold voltage, low-voltage, differential-end, VLSI design
Citation:
Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao, "64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logic," isvlsi, pp.233, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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