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IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04)
A Low Voltage to High Voltage Level Shifter in a Low Voltage, 0.25 ?m, PD SOI Process
Lafayette, Louisiana
February 19-February 20
ISBN: 0-7695-2097-9
Erik J. Mentze, University of Idaho
Kevin M. Buck, University of Idaho
Herbert L. Hess, University of Idaho
David Cox, University of Idaho
Mohammad Mojarradi, California Institute of Technology

This paper describes a low voltage to high voltage logic level shifter that has been designed entirely in a low breakdown voltage process. As such, the scalability of the design to higher output levels has not been restricted by the fabrication process used. Further, to increase the output voltage capability of the design, without altering the fabrication process in any way, the University of Idaho developed high voltage, Laterally Diffused MOSFET (LDMOSFET) is used for the output driver. By combining a unique circuit topology with LDMOSFETs, output voltage levels are achieved that exceed the breakdown voltage of the process used.

A 2.5 - 5 volt implementation of the design is presented, along with a generalization for higher levels. All circuits have been developed in a 2.5 volt breakdown, 0.25?m, partially depleted, silicon-oninsulator, radiation hardened CMOS process.

Citation:
Erik J. Mentze, Kevin M. Buck, Herbert L. Hess, David Cox, Mohammad Mojarradi, "A Low Voltage to High Voltage Level Shifter in a Low Voltage, 0.25 ?m, PD SOI Process," isvlsi, pp.218, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004
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