This paper presents a delay constraint power minimization technique for logic incorporating dual supply voltages. The power is reduced by selecting supply voltage according to switching activity of the subunits. The technique employs energy and delay models of arithmetic units with array structure. The supply voltage is selected to reduce power consumption while maintaining propagation delay constraint. The model characterization is done with Verilog simulation where subunits are designed with Cadence and HSPICE using 0.35 ?m CMOS process. We applied the technique on multiplier of general purpose DSP processors and CORDIC. The results obtained from the proposed method is discussed.