As processing technology continues to evolve, power minimization becomes more complex and crucial. Emerging technologies offer an array of different threshold voltages and gate oxide thicknesses. Along with choices of supply-voltage, parallelism, and pipelining, these options complicate the search for energy-optimal architectures. This paper explores the possibility of using convex optimization to solve the multi-parameter optimization problem and presents a case-study of an 8-bit multiply-accumulate block, which is optimized in 250nm and 70nm technologies.