This paper proposes an energy recovery SRAM that achieves signi.cant dynamic power savings by recovering energy stored in large bit line capacitors. Memory load to power-clock during write is kept fixed by precharging non-selectively after each write cycle. Load during read is also kept fixed by not driving the bit lines with power-clock for read. A simple power-clock generator control scheme that exploits the fixed-load characteristics of the energy recovery memory is introduced to achieve substantially reduced total system power dissipation. The power-clock control scheme reduces system dissipation by preventing the replenishing operation of the power-clock generator while not writing and thus does not require energy transfer between the memory and the power-clock.

Hspice simulations of a full custom 128x256 energy recovery SRAM core show over 4.77x more efficient write operations in comparison with its conventional counterpart at 2.5V, 250MHz. Simulations with a power-clock generator show that disabling power-clock replenishing, whenever memory does not write, achieves savings over 1.47x on total system power over that of a system without the power-clock control.