Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Peter Celinski Articles by Said Al-Sarawi Articles by Derek Abbott Articles by Sorin Cotofana Articles by Stamatis Vassiliadis

IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04)

Lafayette, Louisiana

February 19-February 20

ISBN: 0-7695-2097-9

	ASCII Text	x
	Peter Celinski, Said Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis, "Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach," VLSI, IEEE Computer Society Annual Symposium on, pp. 127, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004.

	BibTex	x
	@article{ 10.1109/ISVLSI.2004.1339519, author = {Peter Celinski and Said Al-Sarawi and Derek Abbott and Sorin Cotofana and Stamatis Vassiliadis}, title = {Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2097-9}, pages = {127}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339519}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach SN - 0-7695-2097-9 SP EP A1 - Peter Celinski, A1 - Said Al-Sarawi, A1 - Derek Abbott, A1 - Sorin Cotofana, A1 - Stamatis Vassiliadis, PY - 2004 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Peter Celinski, University of Adelaide

Said Al-Sarawi, University of Adelaide

Derek Abbott, University of Adelaide

Sorin Cotofana, Delft University of Technology

Stamatis Vassiliadis, Delft University of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339519

This paper presents the design exploration of CMOS 64-bit adders designed using threshold logic gates based on systematic transistor level delay estimation using Logical Effort (LE). The adders are hybrid designs consisting of domino and the recently proposed Charge Recycling Threshold Logic (CRTL). The delay evaluation is based LE modeling of the delay of the domino and CRTL gates. From the initial estimations, we select the 8-bit sparse carry look-ahead/carry-select scheme. Simulations indicate a delay of less than 5 FO4, which is 1.1 FO4 or 17% faster than the nearest domino design.

Citation:

Peter Celinski, Said Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis, "Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach," isvlsi, pp.127, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.