This paper describes a new sampling circuit topology that shapes clock jitter induced sampling noise in much the same way a ΣΔ Analog-to-Digital Converter (ADC) shapes quantization noise. The sampling circuit consists of a continuous-time (CT) integrator followed by two switches. One for the output and one for the feedback. Its intended use is as a front-end for ADCs where jitter is a concern, e.g. wideband or bandpass ΣΔ ADCs. The main benefit of this converter is that its sampling noise due to jitter is, to a large extent, independent of the signal frequency. This means that as the signal frequency increases, and traditional sampling circuits' performance deteriorates, the proposed ΣΔ sampler offers a maintained high sampling accuracy.

Calculations and simulations in this paper show that the ΣΔ sampler has higher performance than a traditional sampling circuit (circuit noise not included), if the main part of the signal power is in the upper portion of the frequency band. The maximum benefit, assuming the input is a single sinusoidal tone, is approximately 4.75 dB in signalto-jitter-noise ratio (SJNR).