IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04)
Fault Tolerant Algorithms for Network-On-Chip Interconnect
Lafayette, Louisiana
February 19-February 20
ISBN: 0-7695-2097-9
As technology scales, fault tolerance is becoming a key concern in on-chip communication. Consequently, this work examines fault tolerant communication algorithms for use in the NoC domain. Two different flooding algorithms and a random walk algorithm are investigated. We show that the flood-based fault tolerant algorithms have an exceedingly high communication overhead. We find that the redundant random walk algorithm offers significantly reduced overhead while maintaining useful levels of fault tolerance. We then compare the implementation costs of these algorithms, both in terms of area as well as in energy consumption, and show that the .ooding algorithms consume an order of magnitude more energy per message transmitted.
Index Terms:
Fault Tolerance, Network on Chip, Random Walk, Flooding
Citation:
M. Pirretti, G. M. Link, R. R. Brooks, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, "Fault Tolerant Algorithms for Network-On-Chip Interconnect," isvlsi, pp.46, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004