HIGH THROUGHPUT POWER-AWARE FIR FILTER DESIGN BASED ON FINE-GRAIN PIPELINING MULTIPLIERS AND ADDERS

I
ISVLSI
2003
IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Abstract - HIGH THROUGHPUT POWER-AWARE FIR FILTER DESIGN BASED ON FINE-GRAIN PIPELINING MULTIPLIERS AND ADDERS

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IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)

HIGH THROUGHPUT POWER-AWARE FIR FILTER DESIGN BASED ON FINE-GRAIN PIPELINING MULTIPLIERS AND ADDERS (PDF)

Tampa, Florida

February 20-February 21

ISBN: 0-7695-1904-0

	ASCII Text	x
	Jia Di, J. S. Yuan, R. Demara, "HIGH THROUGHPUT POWER-AWARE FIR FILTER DESIGN BASED ON FINE-GRAIN PIPELINING MULTIPLIERS AND ADDERS," VLSI, IEEE Computer Society Annual Symposium on, pp. 260, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03), 2003.

	BibTex	x
	@article{ 10.1109/ISVLSI.2003.1183490, author = {Jia Di and J. S. Yuan and R. Demara}, title = {HIGH THROUGHPUT POWER-AWARE FIR FILTER DESIGN BASED ON FINE-GRAIN PIPELINING MULTIPLIERS AND ADDERS}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2003}, isbn = {0-7695-1904-0}, pages = {260}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2003.1183490}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - HIGH THROUGHPUT POWER-AWARE FIR FILTER DESIGN BASED ON FINE-GRAIN PIPELINING MULTIPLIERS AND ADDERS SN - 0-7695-1904-0 SP EP A1 - Jia Di, A1 - J. S. Yuan, A1 - R. Demara, PY - 2003 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Jia Di, University of Central Florida

J. S. Yuan, University of Central Florida

R. Demara, University of Central Florida

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2003.1183490

In regular FIR structure, by pipelining the multipliers one can improve the throughput. But as the growth of operand word length, the delay in addition process becomes another important constraint. In this paper, a novel fine-grain pipelining scheme for high throughput FIR is proposed. By pipelining multipliers and adders, very high throughput can be achieved. 2-Dimensional pipeline gating technique is used to make the designed FIR power aware to the precision of the operands. The average power dissipation and latency are both significantly reduced with changing of input precisions.

Citation:

Jia Di, J. S. Yuan, R. Demara, "HIGH THROUGHPUT POWER-AWARE FIR FILTER DESIGN BASED ON FINE-GRAIN PIPELINING MULTIPLIERS AND ADDERS," isvlsi, pp.260, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03), 2003

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