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IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Tampa, Florida
February 20-February 21
ISBN: 0-7695-1904-0
ASCII Text
x 
 
Bassam Shaer, Kailash Aurangabadkar, Nitin Agarwal, "Testable Sequential Circuit Design:Partitioning for Pseudoexhaustive Test," VLSI, IEEE Computer Society Annual Symposium on, pp. 244, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03), 2003.
 
 
BibTex
x
 
@article{ 10.1109/ISVLSI.2003.1183484,
author = {Bassam Shaer and Kailash Aurangabadkar and Nitin Agarwal},
title = {Testable Sequential Circuit Design:Partitioning for Pseudoexhaustive Test},
journal ={VLSI, IEEE Computer Society Annual Symposium on},
volume = {0},
year = {2003},
isbn = {0-7695-1904-0},
pages = {244},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2003.1183484},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI, IEEE Computer Society Annual Symposium on
TI - Testable Sequential Circuit Design:Partitioning for Pseudoexhaustive Test
SN - 0-7695-1904-0
SP
EP
A1 - Bassam Shaer,
A1 - Kailash Aurangabadkar,
A1 - Nitin Agarwal,
PY - 2003
KW - null
VL - 0
JA - VLSI, IEEE Computer Society Annual Symposium on
ER -
 
Bassam Shaer, Department of Electrical & Computer Engineering, UMD
Kailash Aurangabadkar, Department of Computer Science, UMD
Nitin Agarwal, Department of Computer Science, UMD
In this study, we present an automated algorithm that partitions large sequential VLSI circuits for pseudoexhaustive testing. The partitioning algorithm is based on the primary input cone and fanout value of each node in the circuit. We have developed an optimization process that can be used to find the optimal size of primary input cone and fanout values, to be used for partitioning a given circuit. Experimenta results are presented to demonstrate the effectiveness of our work.
Citation:
Bassam Shaer, Kailash Aurangabadkar, Nitin Agarwal, "Testable Sequential Circuit Design:Partitioning for Pseudoexhaustive Test," isvlsi, pp.244, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03), 2003
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