loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors
Tampa, Florida
February 20-February 21
ISBN: 0-7695-1904-0
Yu Bai, Brown University
R. Iris Bahar, Brown University
In this work we focus on power-aware solutions for the issue queue in an out-of-order superscalar processor. We propose two different schemes. Our first approach partitions the issue queue into FIFOs such that only the instructions at the head of each FIFO may request to issue. We then dynamically monitor the FIFO usage and disable FIFOs that are not being efficiently used. In our second approach we also use a FIFO scheme, but dynamically vary the number and size of each FIFO simultaneously while at the same time keeping the total number of issue queue entries constant. We analyze both approaches and compare them in terms of the performance and power reduction. We find that although the first scheme of completely disabling issue queue entries is more straight-forward to implement, it may not be the best option, particularly for floating point applications. Our best experimental result shows an average power saving of 27.3% in the issue queue with a performance degradation of only 2.7%.
Citation:
Yu Bai, R. Iris Bahar, "A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors," isvlsi, pp.139, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03), 2003
Usage of this product signifies your acceptance of the Terms of Use.