Dissipation in the clock tree and state elements of ASIC designs is often a significant fraction of total energy consumption. We propose methodology for recovering most of this energy by using a novel energy recovering flip-flop and a novel single-phase resonant clock generator. As our state element has near-zero energy consumption when the input data is not switching, it provides the savings of clock gating approaches without the additional complexity of implementing clock gating in the design. To complement this near-zero idle energy property of the flip-flop, our resonant clock generator includes the capability to decide, on a per-cycle basis, whether or not the resonant clock needs to be replenished on the next cycle, thus automatically reducing energy consumption when most of the state elements are idling. ASICs designed with our methodology can achieve sub_C_V²\atop_dd dissipations on the clock network at frequencies of 200-500MHz and operating voltages of 1.0-1.5V in a 0.25?m process. To evaluate our methodology, we simulated a dual-mode (conventional and energy recovering) ASIC module to directly compare energy savings between the energy recovering and conventional clocking schemes. Our simulations demonstrate savings of over a factor of 4 for the energy-recovering mode versus the conventional mode for low switching activities.