A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test

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	Similar Articles Articles by Srdjan Dragic Articles by Martin Margala

IEEE Computer Society Annual Symposium on VLSI (ISVLSI'02)

Pittsburgh, Pennsylvania

April 25-April 26

ISBN: 0-7695-1486-3

	ASCII Text	x
	Srdjan Dragic, Martin Margala, "A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test," VLSI, IEEE Computer Society Annual Symposium on, pp. 0165, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'02), 2002.

	BibTex	x
	@article{ 10.1109/ISVLSI.2002.1016891, author = {Srdjan Dragic and Martin Margala}, title = {A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2002}, isbn = {0-7695-1486-3}, pages = {0165}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2002.1016891}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test SN - 0-7695-1486-3 SP EP A1 - Srdjan Dragic, A1 - Martin Margala, PY - 2002 KW - Current Monitoring KW - Iddq KW - delta Iddq KW - On-Line Testing KW - Current Amplifier VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Srdjan Dragic, University of Alberta

Martin Margala, University of Rochester

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2002.1016891

A novel low-voltage design of Iddq/delta Iddq architecture suitable for a Built-In-Self-Test (BIST) implementation with analog, digital or mixed-signal cores is proposed. In testing mode, the architecture performs a non-functional Iddq and delta Iddq test which enables more accurate fail/pass decision. A 1.2V high-frequency current amplifying cell is developed as a central part of the Iddq/delta Iddq current monitor. With sensitivity of less than 200nA, the monitor achieves a gain-bandwidth product of 6.8GHz, a low frequency current gain of 48dB, and a high linearity for input current range (-15?A, 15?A). Its functionality and high performances are verified in experimental simulations. The Iddq fault detector has been implemented in 0.13?m CMOS technology with 1.2V power supply.

Index Terms:

Current Monitoring, Iddq, delta Iddq, On-Line Testing, Current Amplifier

Citation:

Srdjan Dragic, Martin Margala, "A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test," isvlsi, pp.0165, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'02), 2002

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