As cost-effective approach to develop special-purpose processors, field programmable gate arrays (FPGAs) are widely used. However, their major disadvantage is their low performance because of large delays of programmable interconnection networks. This paper proposes a high-performance field programmable VLSI processor (FPVLSI). A bit-serial PE array is presented to reduce complexity of programmable interconnection networks. Therefore, the area and the delay of a switch block in the interconnection network can be greatly reduced. Moreover, a direct allocation of a control/data flow graph is employed where only a single node is mapped into a PE so that the wiring complexity is greatly reduced. The FPVLSI with 4400 PEs is designed in a 0.35um CMOS process. The performance of the FPVLSI is evaluated to be 28 times higher than that of the typical FPGA when executing the 16-point FFT.