An Object-Oriented Design Process for System-on-Chip Using UML

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Proceedings of the 15th international symposium on System Synthesis (ISSS '02)

Kyoto, Japan

October 02-October 04

ISBN: 1-58113-576-9

	ASCII Text	x
	Tsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya Kuwamura, Qiang Zhu, "An Object-Oriented Design Process for System-on-Chip Using UML," System Synthesis, International Symposium on, pp. 249-254, Proceedings of the 15th international symposium on System Synthesis (ISSS '02), 2002.

	BibTex	x
	@article{ 10.1109/ISSS.2002.1227186, author = {Tsuneo Nakata and Akio Matsuda and Minoru Shoji and Shinya Kuwamura and Qiang Zhu}, title = {An Object-Oriented Design Process for System-on-Chip Using UML}, journal ={System Synthesis, International Symposium on}, volume = {0}, year = {2002}, isbn = {1-58113-576-9}, pages = {249-254}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISSS.2002.1227186}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - System Synthesis, International Symposium on TI - An Object-Oriented Design Process for System-on-Chip Using UML SN - 1-58113-576-9 SP249 EP254 A1 - Tsuneo Nakata, A1 - Akio Matsuda, A1 - Minoru Shoji, A1 - Shinya Kuwamura, A1 - Qiang Zhu, PY - 2002 KW - UML KW - design process KW - object-oriented analysis and design KW - system level design KW - system level performance evaluation VL - 0 JA - System Synthesis, International Symposium on ER -

Tsuneo Nakata, Fujitsu Laboratories Limited, Kawasaki 211-8588, Japan

Akio Matsuda, Fujitsu Laboratories Limited, Kawasaki 211-8588, Japan

Minoru Shoji, Fujitsu Limited, Kawasaki 211-8588, Japan

Shinya Kuwamura, Fujitsu Laboratories Limited, Kawasaki 211-8588, Japan

Qiang Zhu, Fujitsu Laboratories Limited, Kawasaki 211-8588, Japan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISSS.2002.1227186

The object-oriented design process has been a hot topic in software development since it will improve product quality and productivity significantly, which is also a major issue in system-on-chip design. In this paper, a design process is proposed for hardware-software heterogeneous systems by reinforcing parallelism, structure, and timing. The management of design abstraction is also introduced for refinement of hardware. UML is used as a modeling language, and the reinforcement above is gracefully integrated into UML by its extensibility mechanism. An example of architecture exploration and performance analysis is illustrated through the application of the process to an image decoding design.

Index Terms:

UML, design process, object-oriented analysis and design, system level design, system level performance evaluation

Citation:

Tsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya Kuwamura, Qiang Zhu, "An Object-Oriented Design Process for System-on-Chip Using UML," isss, pp.249-254, Proceedings of the 15th international symposium on System Synthesis (ISSS '02), 2002

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