Modeling Assembly Instruction Timing in Superscalar Architectures

	This Article
	Subscribers, please Login Purchase article: $19 PDF RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by W. Fornaciari Articles by V. Trianni Articles by C. Brandolese Articles by D. Sciuto Articles by F. Salice Articles by G. Beltrame

Proceedings of the 15th international symposium on System Synthesis (ISSS '02)

Kyoto, Japan

October 02-October 04

ISBN: 1-58113-576-9

	ASCII Text	x
	W. Fornaciari, V. Trianni, C. Brandolese, D. Sciuto, F. Salice, G. Beltrame, "Modeling Assembly Instruction Timing in Superscalar Architectures," System Synthesis, International Symposium on, pp. 132-137, Proceedings of the 15th international symposium on System Synthesis (ISSS '02), 2002.

	BibTex	x
	@article{ 10.1109/ISSS.2002.1227165, author = {W. Fornaciari and V. Trianni and C. Brandolese and D. Sciuto and F. Salice and G. Beltrame}, title = {Modeling Assembly Instruction Timing in Superscalar Architectures}, journal ={System Synthesis, International Symposium on}, volume = {0}, year = {2002}, isbn = {1-58113-576-9}, pages = {132-137}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISSS.2002.1227165}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - System Synthesis, International Symposium on TI - Modeling Assembly Instruction Timing in Superscalar Architectures SN - 1-58113-576-9 SP132 EP137 A1 - W. Fornaciari, A1 - V. Trianni, A1 - C. Brandolese, A1 - D. Sciuto, A1 - F. Salice, A1 - G. Beltrame, PY - 2002 KW - assembly-level analysis KW - performance estimation KW - superscalar architectures VL - 0 JA - System Synthesis, International Symposium on ER -

W. Fornaciari, Politecnico di Milano, Piazza L. da Vinci, Milano, Italy

V. Trianni, Politecnico di Milano, Piazza L. da Vinci, Milano, Italy

C. Brandolese, Politecnico di Milano, Piazza L. da Vinci, Milano, Italy

D. Sciuto, Politecnico di Milano, Piazza L. da Vinci, Milano, Italy

F. Salice, Politecnico di Milano, Piazza L. da Vinci, Milano, Italy

G. Beltrame, CEFRIEL Research Centre, Via R. Fucini, Milano, Italy

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISSS.2002.1227165

This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provides a methodology and a toolset to perform data analysis and model tuning. The methodology also provides a framework for building new trace simulators for generic architectures. The results obtained show a good accuracy paired with a satisfactory computational efficiency.

Index Terms:

assembly-level analysis, performance estimation, superscalar architectures

Citation:

W. Fornaciari, V. Trianni, C. Brandolese, D. Sciuto, F. Salice, G. Beltrame, "Modeling Assembly Instruction Timing in Superscalar Architectures," isss, pp.132-137, Proceedings of the 15th international symposium on System Synthesis (ISSS '02), 2002

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.