System-Level Design of IEEE1394 Bus Segment Bridge

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Proceedings of the 15th international symposium on System Synthesis (ISSS '02)

Kyoto, Japan

October 02-October 04

ISBN: 1-58113-576-9

	ASCII Text	x
	Takao Onoye, Yukihiro Nakamura, Atsuhito Shigiya, Keishi Chikamura, Kosuke Tsujino, Tomonori Izumi, Hirofumi Yamamoto, "System-Level Design of IEEE1394 Bus Segment Bridge," System Synthesis, International Symposium on, pp. 74-79, Proceedings of the 15th international symposium on System Synthesis (ISSS '02), 2002.

	BibTex	x
	@article{ 10.1109/ISSS.2002.1227155, author = {Takao Onoye and Yukihiro Nakamura and Atsuhito Shigiya and Keishi Chikamura and Kosuke Tsujino and Tomonori Izumi and Hirofumi Yamamoto}, title = {System-Level Design of IEEE1394 Bus Segment Bridge}, journal ={System Synthesis, International Symposium on}, volume = {0}, year = {2002}, isbn = {1-58113-576-9}, pages = {74-79}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISSS.2002.1227155}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - System Synthesis, International Symposium on TI - System-Level Design of IEEE1394 Bus Segment Bridge SN - 1-58113-576-9 SP74 EP79 A1 - Takao Onoye, A1 - Yukihiro Nakamura, A1 - Atsuhito Shigiya, A1 - Keishi Chikamura, A1 - Kosuke Tsujino, A1 - Tomonori Izumi, A1 - Hirofumi Yamamoto, PY - 2002 KW - C/C++ KW - HW/SW co-simulation KW - IEEE1394 KW - PLI KW - bus bridge KW - verilog-HDL VL - 0 JA - System Synthesis, International Symposium on ER -

Takao Onoye, Kyoto University, Kyoto, Japan

Yukihiro Nakamura, Kyoto University, Kyoto, Japan

Atsuhito Shigiya, Kyoto University, Kyoto, Japan

Keishi Chikamura, Kyoto University, Kyoto, Japan

Kosuke Tsujino, Kyoto University, Kyoto, Japan

Tomonori Izumi, Kyoto University, Kyoto, Japan

Hirofumi Yamamoto, Kyoto University, Kyoto, Japan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISSS.2002.1227155

A system simulation environment is constructed dedicatedly for IEEE1394 high-speed digital communication. In this environment, various network transactions inherent in communication systems are taken into account for system simulation, which is indispensable to enable IP (Intellectual Property)-based design of the systems. By using the proposed environment, system-level design of IEEE1394 link layer controller and bus segment bridge is achieved with great ability of network transactions as well as connectivities with physical layer chips. Functionalities of the designed bus segment bridge has been verified according to its FPGA implementation.

Index Terms:

C/C++, HW/SW co-simulation, IEEE1394, PLI, bus bridge, verilog-HDL

Citation:

Takao Onoye, Yukihiro Nakamura, Atsuhito Shigiya, Keishi Chikamura, Kosuke Tsujino, Tomonori Izumi, Hirofumi Yamamoto, "System-Level Design of IEEE1394 Bus Segment Bridge," isss, pp.74-79, Proceedings of the 15th international symposium on System Synthesis (ISSS '02), 2002

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