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Proceedings of the 15th international symposium on System Synthesis (ISSS '02)
Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design
Kyoto, Japan
October 02-October 04
ISBN: 1-58113-576-9
Ahmed A. Jerraya, Laboratoire TIMA, Grenoble cedex, France
Damien Lyonnard, Laboratoire TIMA, Grenoble cedex, France
Samy Meftali, Laboratoire TIMA, Grenoble cedex, France
Fr?d?ric Rousseau, Laboratoire TIMA, Grenoble cedex, France
F?rid Gharsalli, Laboratoire TIMA, Grenoble cedex, France
In this paper, we present a new methodology for application specific multiprocessor system-on-chip design. This approach facilitates the integration of existing components with the concept of wrapper. Wrappers allow automatic adaptation of physical interfaces to a communication network. We also give a generic architecture to produce these wrappers, either for processors or for other specific components such as memory IP. This approach has successfully been applied on a low-level image processing application.
Index Terms:
embedded memory, memory access, memory wrapper generation, system-on-chip
Citation:
Ahmed A. Jerraya, Damien Lyonnard, Samy Meftali, Fr?d?ric Rousseau, F?rid Gharsalli, "Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design," isss, pp.26-31, Proceedings of the 15th international symposium on System Synthesis (ISSS '02), 2002
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