Efficient use of an optimized custom memory hierarchy to exploit temporal locality in the memory accesses on array signals can have a very large impact on the power consumption in embedded data dominated applications. Only recently effective formalized techniques to deal with this specific task have been addressed. They work well for homogeneous signal access patterns but cannot handle other cases. In this paper, we will extend and parameterize the design space and establish heuristics for an efficient exploration, such that better results in terms of area and power can be achieved for applications where holes are present in the signal access pattern. The extended methodology will be illustrated for several real-life image-processing algorithms.