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13th International Symposium on System Synthesis (ISSS'00)
Hierarchical Conditional Dependency Graphs as a Unifying Design Representation in the CODESIS High-Level Synthesis System
Madrid, Spain
September 20-September 22
ISBN: 0-7695-0765-4
Apostolos A. Kountouris, Mitsubishi Electric ITE
Christophe Wolinski, Universitaire de Beaulieu
In high-level hardware, synthesis (HLS) there is a gap on the quality of the synthesized results between data-flow and control-flow dominated behavioral descriptions. Heuristics destined for the former usually perform poorly on the latter. To close this gap, the CODESIS interactive HLS tool relies on a unifying intermediate design representation and adapted heuristics that are able to accommodate both types of designs as well as designs of a mixed data-flow and control-flow nature. Preliminary experimental results in mutual exclusiveness detection and in efficiently scheduling conditional behaviors are encouraging and prompt for experimentation that is more extensive.
Citation:
Apostolos A. Kountouris, Christophe Wolinski, "Hierarchical Conditional Dependency Graphs as a Unifying Design Representation in the CODESIS High-Level Synthesis System," isss, pp.66, 13th International Symposium on System Synthesis (ISSS'00), 2000
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