In order to speed up current DSP applications, complex hardware accelerators may be added in DSP architectures. This means that “coarse-grain” operations, characterized by a long latency and by a complex Input-Output timeshape, may be available to implement the given application. In a traditional scheduling approach, course-grain operations are treated as bulky atomic multi-cycle operations, under the worst-case assumption that inputs and output are confined at the beginning and at the end of the operation itself. In this paper, we propose a novel scheduling method for VLIW processors, where coarse-grain operations are decomposed into a number of fine Input and Output operations. Therefore, each I/O operation is scheduled separately in order to synchronize data communication among operations in a “Just in Time” fashion. This leads to a higher Instruction Level Parallelism (ILP) in the processor, and decreases the number of registers needed in the architecture. The experiments show that embedding custom hardware accelerators in a VLIW datapath, as proposed in this paper, enhances performances keeping the VLIW controller's microcode width small.