5th International Symposium on Quality Electronic Design (ISQED'04) Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels San Jose, California March 22-March 24 ISBN: 0-7695-2093-6
ESD protection design for mixed-voltage I/O interfaces with the low-voltage-triggered PNP (LVTPNP) devices is proposed in this paper. The LVTPNP, by inserting N+ or P+ diffusion across the junction between N-well and P-substrate of the PNP devices, is designed to protect the mixed-voltage I/O pads for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (under-VSS). The experimental results in a 0.35-?m CMOS process have proven that the ESD level of the proposed LVTPNP is higher than that of the traditional PNP device.
Citation:
Ming-Dou Ker, Wei-Jen Chang, Wen-Yu Lo, "Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels," isqed, pp.433-438, 5th International Symposium on Quality Electronic Design (ISQED'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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