5th International Symposium on Quality Electronic Design (ISQED'04)
Stacked FSMD: A Power Efficient Micro-Architecture for High Level Synthesis
San Jose, California
March 22-March 24
ISBN: 0-7695-2093-6
In this paper, we argue that the classic micro-architecture model, namely finite state machine with datapath (FSMD), cannot handle procedure abstraction needed by complex applications. This presents one of the major obstacles for the adoption of high-level synthesis technology in practice. We propose a simple extension of FSMD, called stacked FSMD, which mimics the procedure linkage concepts in software. We demonstrate that the new micro-architecture can not only fully support procedure calls, but also be made power efficient by a technique called region-based partitioning, which can be applied directly at the behavioral level with the assistance of simple metric evaluated at the behavioral level. With a rigorous experimental procedure, we show that the controller power saving achieved can range from 12% to 68% with modest overhead in area.
Citation:
Khushwinder Jasrotia, Jianwen Zhu, "Stacked FSMD: A Power Efficient Micro-Architecture for High Level Synthesis," isqed, pp.425-430, 5th International Symposium on Quality Electronic Design (ISQED'04), 2004