Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates

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5th International Symposium on Quality Electronic Design (ISQED'04)

San Jose, California

March 22-March 24

ISBN: 0-7695-2093-6

	ASCII Text	x
	Ge Yang, Zhongda Wang, Sung-Mo Kang, "Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates," Quality Electronic Design, International Symposium on, pp. 421-424, 5th International Symposium on Quality Electronic Design (ISQED'04), 2004.

	BibTex	x
	@article{ 10.1109/ISQED.2004.1283710, author = {Ge Yang and Zhongda Wang and Sung-Mo Kang}, title = {Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2004}, issn = {2003116307}, pages = {421-424}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2004.1283710}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates SN - 2003116307 SP421 EP424 A1 - Ge Yang, A1 - Zhongda Wang, A1 - Sung-Mo Kang, PY - 2004 KW - null VL - 0 JA - Quality Electronic Design, International Symposium on ER -

Ge Yang, University of California at Santa Cruz

Zhongda Wang, University of California at Santa Cruz

Sung-Mo Kang, University of California at Santa Cruz

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2004.1283710

Domino keeper has to be upsized to keep the noise margin in high fan-in dynamic gates, which increases the power consumption and slows down the evaluation. We propose a four-phase non-full swing keeper design to solve this dilemma. Non-full swing switching at the keeper gate together with alleviated contention help to reduce power consumption and delay. Simulation of 16-input OR gate using 0.13um CMOS SPICE parameters shows that proposed keeper design can reduce power consumption and delay by 26% and 24%, respectively.

Citation:

Ge Yang, Zhongda Wang, Sung-Mo Kang, "Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates," isqed, pp.421-424, 5th International Symposium on Quality Electronic Design (ISQED'04), 2004

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