Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies

I
ISQED
2004
5th International Symposium on Quality Electronic Design (ISQED'04)
Abstract - Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies

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5th International Symposium on Quality Electronic Design (ISQED'04)

San Jose, California

March 22-March 24

ISBN: 0-7695-2093-6

	ASCII Text	x
	Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy, "Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies," Quality Electronic Design, International Symposium on, pp. 415-420, 5th International Symposium on Quality Electronic Design (ISQED'04), 2004.

	BibTex	x
	@article{ 10.1109/ISQED.2004.1283709, author = {Bhaskar Chatterjee and Manoj Sachdev and Ram Krishnamurthy}, title = {Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2004}, issn = {2003116307}, pages = {415-420}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2004.1283709}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies SN - 2003116307 SP415 EP420 A1 - Bhaskar Chatterjee, A1 - Manoj Sachdev, A1 - Ram Krishnamurthy, PY - 2004 KW - null VL - 0 JA - Quality Electronic Design, International Symposium on ER -

Bhaskar Chatterjee, University of Waterloo

Manoj Sachdev, University of Waterloo

Ram Krishnamurthy, Intel Corporation

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2004.1283709

In this paper, we discuss the design of leakage tolerant wide-OR domino gates for deep submicron (DSM), bulk CMOS technologies. Technology scaling is resulting in 3-5x increase in transistor I_OFF/?m per generation resulting in 15%-30% noise margin degradation of high performance domino gates. We investigate several techniques that can improve the noise margin of domino logic gates and thereby ensure their reliable operation for sub-130nm technologies. Our simulations indicate that, selective usage of dual V_TH transistors shows acceptable energy-delay tradeoffs for the 90nm technology. However, techniques like supply voltage (V_cc) reduction and using non-minimum L_e transistors are required in order to ensure robust and scalable wide-OR domino designs for the 70nm generation.

Citation:

Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy, "Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies," isqed, pp.415-420, 5th International Symposium on Quality Electronic Design (ISQED'04), 2004

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