Rapid advances in VLSI technology have enabled shrinking feature sizes, wire widths, and wire spacings making the effects of coupling capacitance more apparent. As signals switch faster, noise due to coupling between neighboring wires becomes more pronounced. Changing relative signal arrival times alters the victim line delay due to the varying coupling noise on the victim line. We propose a sensitivity based method to analyze delay uncertainties of coupled interconnects due to uncertain signal arrival times at its inputs. Our simulation results show that the proposed method strikes a good balance between model accuracy and complexity compared to the existing approaches.