Pattern-sensitive soft errors, subject to varied supply and substrate noises, have become increasingly significant for configurable memories embedded in SoCs. In this paper, we study their effects on memory cell, array, and circuit design. It is found that the ground bounce reduces the cell current more severely than the supply voltage drop and substrate bias dip. This encourages the use of metal wires along the wordline or row direction. Bitline tracking by current ratio achieves better accuracy and design for manufacturing (DFM) capability than by capacitance ratio. It requires further enhancement to be resilient to the supply and substrate noises. The proposed dynamic tracking cluster technique provides necessary timing relaxation, while minimizing the speed degradation. Configurable embedded SRAM and ROM in 0.18?m CMOS process are studied.