Copper (Cu) based interconnect technology is expected to meet some of the challenges of technology scaling in the pursuit of higher performance. However, Cu interconnects are still susceptible to electromigration-induced failure over time. We describe a new hierarchical approach for predicting the reliability of Cu-based interconnects in circuit layouts, and present an RCAD tool, SysRel, for such an analysis. We propose a (jL) product filtering algorithm with a classification of separate via-above and via-below treatments in Cu interconnect trees. After the filtering of immortal trees, a default model is applied to the remaining trees to compute reliability figures for individual units. SysRel utilizes joint stochastic reliability metrics based on the desired lifetime of a chip and combines reliability figures from individual fundamental reliability units. Simulation results with a 32-bit comparator circuit layout demonstrate the significance of our methodology in selectively identifying critical nets and their impacts on overall reliability.