A Clustering Based Area I/O Planning for Flip-Chip Technology

I
ISQED
2004
5th International Symposium on Quality Electronic Design (ISQED'04)
Abstract - A Clustering Based Area I/O Planning for Flip-Chip Technology

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5th International Symposium on Quality Electronic Design (ISQED'04)

San Jose, California

March 22-March 24

ISBN: 0-7695-2093-6

	ASCII Text	x
	Janet Wang, Kishore Kumar Muchherla, Jai Ganesh Kumar, "A Clustering Based Area I/O Planning for Flip-Chip Technology," Quality Electronic Design, International Symposium on, pp. 196-201, 5th International Symposium on Quality Electronic Design (ISQED'04), 2004.

	BibTex	x
	@article{ 10.1109/ISQED.2004.1283673, author = {Janet Wang and Kishore Kumar Muchherla and Jai Ganesh Kumar}, title = {A Clustering Based Area I/O Planning for Flip-Chip Technology}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2004}, issn = {2003116307}, pages = {196-201}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2004.1283673}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - A Clustering Based Area I/O Planning for Flip-Chip Technology SN - 2003116307 SP196 EP201 A1 - Janet Wang, A1 - Kishore Kumar Muchherla, A1 - Jai Ganesh Kumar, PY - 2004 KW - null VL - 0 JA - Quality Electronic Design, International Symposium on ER -

Janet Wang, University of Arizona at Tucson

Kishore Kumar Muchherla, University of Arizona at Tucson

Jai Ganesh Kumar, University of Arizona at Tucson

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2004.1283673

The complexity of nanometer SoC design requires the codesign and development of circuit design and packaging technology to enable a successful 'total integrated solution'. In this paper we introduce a new area I/O algorithm for the recent flip-chip packaging technology. The algorithm combines a clustering technique with area I/O planning algorithm to avoid iterations during "placement and area I/O pad assignment". Experiment results show that the total interconnect length (including both on-chip and off-chip parts) and delay are reduced by 10-15% comparing with traditional algorithms.

Citation:

Janet Wang, Kishore Kumar Muchherla, Jai Ganesh Kumar, "A Clustering Based Area I/O Planning for Flip-Chip Technology," isqed, pp.196-201, 5th International Symposium on Quality Electronic Design (ISQED'04), 2004

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