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5th International Symposium on Quality Electronic Design (ISQED'04)
Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics
San Jose, California
March 22-March 24
ISBN: 0-7695-2093-6
ASCII Text
x 
 
Meigen Shen, Li-Rong Zheng, Hannu Tenhunen, "Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics," Quality Electronic Design, International Symposium on, pp. 184-189, 5th International Symposium on Quality Electronic Design (ISQED'04), 2004.
 
 
BibTex
x
 
@article{ 10.1109/ISQED.2004.1283671,
author = {Meigen Shen and Li-Rong Zheng and Hannu Tenhunen},
title = {Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2004},
issn = {2003116307},
pages = {184-189},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2004.1283671},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics
SN - 2003116307
SP184
EP189
A1 - Meigen Shen,
A1 - Li-Rong Zheng,
A1 - Hannu Tenhunen,
PY - 2004
KW - null
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
Meigen Shen, Royal Institute of Technology
Li-Rong Zheng, Royal Institute of Technology
Hannu Tenhunen, Royal Institute of Technology
Low interaction between chip and package has more and more limited system performance. In this paper, chip-package co-design flow is presented. We address robustness enhancement under package and interconnection constraints by using impedance control, optimal package pins assignment and transmitter equalization. From the high-speed transmitter design example, co-design can reduce signal integrity problem, enhance its bandwidth, and improve high-speed electronic systems robustness.
Citation:
Meigen Shen, Li-Rong Zheng, Hannu Tenhunen, "Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics," isqed, pp.184-189, 5th International Symposium on Quality Electronic Design (ISQED'04), 2004
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