As the foundries accelerate their update of advanced processes with increasingly complex design rules, the cost of hard intellectual property (IP) development becomes prohibitively high. Automated layout migration techniques used today, which are based on layout compaction developed a decade ago, corrupt advanced design considerations by honoring only design rules. In this paper, we present two new theoretical results: First, we propose a fast constraint generation algorithm proven to be linear, a step forward from the worst case quadratic complexity achieved in the literature. Second, we propose a new optimization metric, called geometric closessness, that can help retain advanced design intention. A layout migration engine based on these two results is implemented and integrated into a comprehensive hard IP development framework, under which the Berkeley low power libraries, originally developed for 1.2um MOSIS process, are successfully migrated into TSMC 0.25um and 0.18um technologies.