Welcome Notes

Organizing Committee (PDF)

pp. xvii

Steering/Advisory Committee (PDF)

pp. xix

Technical Subcommittees (PDF)

pp. xx

Conference at a Glance (PDF)

pp. 3

Integrating Yield, Test and Reliability: "Statistical Models with Applications to Test and Burn-in Optimization" (PDF)

ISQED TUTORIALS

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Tutorial Track A: Design for Yield Optimization and Test

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pp. 7

Optimizing the Yield of VLSI Circuits (PDF)

pp. 7

Tutorial Track B: Design for Manufacturing and Yield

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Testing and Yield of Integrated Circuits (PDF)

pp. 8

Test Structures for Circuit Yield Assessment and Modeling (PDF)

pp. 8

Design Based Yield Improvements (DBYI) (PDF)

pp. 9

Yield in flash memory: Methodology, modeling and design issues (PDF)

pp. 9

Enhancing the Silicon-Package Interface Through Their Concurrent Design and Verification (PDF)

Tutorial Track C: IC and Package Co-Design

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pp. 10

A Package Design Perspective, "It will be BGA and Flip-Chip (PDF)

pp. 10

An IC Design Perspective, "Why Would We Choose Flip Chip? (PDF)

pp. 11

An EDA Perspective, "We Need it Yesterday! (PDF)

pp. 11

An EDA Perspective, "Let?s do it Concurrently! (PDF)

pp. 11

Overview of Reliability Issues in Deep Sub-Micron Digital CMOS Technology and Their Interaction with Circuit Design Considerations (PDF)

Tutorial Track D: Design for Reliability

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pp. 12

Noise Analysis for 0.13um and Beyond (PDF)

pp. 12

NBTI/HCI Modeling and Full-Chip Analysis in Design Environment (PDF)

pp. 13

Is Quality a Design Constraint for Sub 100nm Designs? (PDF)

pp. 15

Plenary Session I

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Platform Leadership in the Ambient Intelligence Era (PDF)

pp. 21

Quality SoC Design and Implementation for Real Manufacturability (PDF)

pp. 23

Quality Challenges of the Nanometer Design Realm (PDF)

pp. 25

Session 1A: Reliability and Design in Deep Submicron Technologies

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Reliability Evaluation for Integrated Circuit with Defective Interconnect under Electromigration (Abstract)

Xiangdong Xuan, Georgia Institute of Technology

Adit D. Singh, Auburn University

Abhijit Chatterjee, Georgia Institute of Technology

pp. 29

PDF

Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs (Abstract)

Amir H. Ajami, University of Southern California

Kaustav Banerjee, University of California at Santa Barbara

Amit Mehrotra, University of Illinois at Urbana-Champaign

Massoud Pedram, University of Southern California

pp. 35

PDF

Random Sampling for On-Chip Characterization of Standard-Cell Propagation Delay (Abstract)

S. Maggioni, STMicroelectronics

A. Veggetti, STMicroelectronics

A. Bogliolo, University of Urbino

L. Croce, University of Urbino

pp. 41

PDF

Session 1B: Reducing Leakage Currents in VLSI Circuits

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Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains (Abstract)

Afshin Abdollahi, University of Southern California

Farzan Fallah, Fujitsu Laboratories of America

Massoud Pedram, University of Southern California

pp. 49

PDF

Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic (Abstract)

Geun Rae Cho, Colorado State University

Tom Chen, Colorado State University

pp. 55

PDF

Design Techniques for Gate-Leakage Reduction in CMOS Circuits (Abstract)

Rafik S. Guindi, University of Toronto

Farid N. Najm, University of Toronto

pp. 61

PDF

Session 1C: SoC Methodology

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Using Integer Equations for High Level Formal Verification Property Checking (Abstract)

Bijan Alizadeh, University of Tehran

Mohammad R. Kakoee, University of Tehran

pp. 69

PDF

True Coverage:A Goal of Verification (Abstract)

Gary Feierbach, Apple Computer, Inc.

Vijay Gupta, Apple Computer, Inc.

pp. 75

PDF

Low-Cost and Real-Time Super-Resolution over a Video Encoder IP (Abstract)

Gustavo M. Callicó, Applied Microelectronics Research Institute

Antonio Núñez, Applied Microelectronics Research Institute

Rafael Peset Llopis, Philips Consumers Electronics

Ramanathan Sethuraman, Philips Research Laboratories Eindhoven

pp. 79

PDF

LYS: A Solution for System on Chip (SoC) Production Cost and Time to Volume Reduction (Abstract)

Jean-Pierre HELIOT, STMicroelectronics

Florent Parmentier, STMicroelectronics

Marie-Pierre Baron, STMicroelectronics

pp. 85

PDF

Session 2A: Testing of SoCs

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Solving the SoC Test Scheduling Problem Using Network Flow and Reconfigurable Wrappers (Abstract)

Sandeep Koranne, Tanner Research Inc.

pp. 93

PDF

Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets (Abstract)

Yu Huang, Mentor Graphics Corporation

Wu-Tung Cheng, Mentor Graphics Corporation

Chien-Chung Tsai, Mentor Graphics Corporation

Nilanjan Mukherjee, Mentor Graphics Corporation

Sudhakar M. Reddy, University of Iowa

pp. 99

PDF

Compact Dictionaries for Fault Diagnosis in BIST (Abstract)

Chunsheng Liu, Duke University

Krishnendu Chakrabarty, Duke University

pp. 105

PDF

Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns (Abstract)

Chien-In Henry Chen, Wright State University

Kiran George, Wright State University

pp. 111

PDF

Session 2B: Design for Manufacturability and Quality

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Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability (Abstract)

F. Duan, LSI Logic Corporation

R. Castagnetti, LSI Logic Corporation

R. Venkatraman, LSI Logic Corporation

O. Kobozeva, LSI Logic Corporation

S. Ramesh, LSI Logic Corporation

pp. 119

PDF

Advanced Physical Models for Mask Data Verification and Impacts on Physical Layout Synthesis (Abstract)

Qi-De Qian, IC Scope Research

Sheldon X.-D. Tan, University of California, Riverside

pp. 125

PDF

New DFM Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains (Abstract)

Pradiptya Ghosh, Numerical Technologies

Chung-shin Kang, Numerical Technologies

Michael Sanie, Numerical Technologies

David Pinto, Numerical Technologies

pp. 131

PDF

System and Framework for QA of Process Design Kits (Abstract)

M. C. Scott, Texas Instruments

M. O. Peralta, Texas Instruments

J. D. Carothers, University of Arizona

pp. 138

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The iFlow Design Factory: Evolving Chip Design from an Art to a Process, through Adaptive Resource Management, and Qualified Data Exchange (Abstract)

Gilles-Eric Descamps, Silicon Access Networks

Satish Bagalkotkar, Silicon Access Networks

Subramanian Ganesan, Silicon Access Networks

Sridhar Subramaniam, Silicon Access Networks

Hem Hingarh, Silicon Access Networks

pp. 144

PDF

Session 2C: Invited Papers Session-Design Considerations in Advanced Technology

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Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits (Abstract)

C. T. Chuang, IBM T. J. Watson Research Center

R. V. Joshi, IBM T. J. Watson Research Center

R. Puri, IBM T. J. Watson Research Center

K. Kim, IBM T. J. Watson Research Center

pp. 153

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Revisiting the Noise Figure Design Metric for Digital Communication Receiver (Abstract)

Won Namgoong, University of Southern California

Jongrit Lerdworatawee, University of Southern California

pp. 159

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Benchmarks for Interconnect Parasitic Resistance and Capacitance (Abstract)

Nagaraj NS, Texas Instruments Inc.

Tom Bonifield, Texas Instruments Inc.

Abha Singh, Texas Instruments Inc.

Frank Cano, Texas Instruments Inc.

Usha Narasimha, Texas Instruments Inc.

Mak Kulkarni, Texas Instruments Inc.

Poras Balsara, University of Texas at Dallas

Cyrus Cantrell, University of Texas at Dallas

pp. 163

PDF

Session 3A: Interconnect and Substrate Noise

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Post-Route Gate Sizing for Crosstalk Noise Reduction (Abstract)

Murat R. Becer, Motorola Inc.

David Blaauw, Univ. of Michigan Ann Arbor

Ilan Algor, Motorola Inc.

Rajendran Panda, Motorola Inc.

Chanhee Oh, Motorola Inc.

Vladimir Zolotov, Motorola Inc.

Ibrahim N. Hajj, Univ. of Illinois Urbana-Champaign

pp. 171

PDF

Noise-Aware Driver Modeling for Nanometer Technology (Abstract)

Xiaoliang Bai, University of California, San Diego

Rajit Chandra, University of California, San Diego

Sujit Dey, University of California, San Diego

P. V. Srinivas, University of California, San Diego

pp. 177

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Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics (Abstract)

Tom Chen, System VLSI Technology Division, HP

Amjad Hajjar, Colorado State University

pp. 183

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Modeling Crosstalk Induced Delay (Abstract)

Chung-Kuan Tsai, University of California, Santa Barbara

Malgorzata Marek-Sadowska, University of California, Santa Barbara

pp. 189

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A CAD-Oriented Modeling Approach of Frequency-Dependent Behavior of Substrate Noise Coupling for Mixed-Signal IC Design (Abstract)

Hai Lan, Stanford University

Zhiping Yu, Stanford University

Robert W. Dutton, Stanford University

pp. 195

PDF

Assessment of the OpenAccess Standard: Insights on the new EDA Industry Standard from Hewlett-Packard, a Beta Partner and Contributing Developer (Abstract)

Session 3B: Impact of New Standards for Design Data Modeling and Manufacturing Interface

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Terry Blanchard, Hewlett-Packard Company

pp. 203

PDF

Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint (Abstract)

Andrew B. Kahng, University of California, San Diego

Igor L. Markov, The University of Michigan

pp. 208

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Interoperability Beyond Design: Sharing Knowledge between Design and Manufacturing (Abstract)

D.R. Cottrell, Si2

T.J. Grebinski, SEMI Data Path Task Force Chair

pp. 214

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Session 3C: Package-Design Interface Challenges

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Advanced Module Packaging Method (Abstract)

Peter C. Salmon, SysFlex

pp. 223

PDF

Electrical and Thermal Analysis for System-in-a-Package (SiP) Implementation Platform (Abstract)

Michael Wang, University of California, Santa Cruz

Katsuharu Suzuki, University of California, Santa Cruz

Wayne Dai, University of California, Santa Cruz

pp. 229

PDF

Modeling and Analysis of Power Distribution Networks for Gigabit Applications (Abstract)

Wendemagegnehu Beyene, Rambus Inc.

Chuck Yuan, Rambus Inc.

Joong-Ho Kim, Rambus Inc.

Madhavan Swaminathan, Rambus Inc.

pp. 235

PDF

Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC (Abstract)

Ming-Dou Ker, National Chiao-Tung University

Jeng-Jie Peng, Industrial Technology Research Institute

Hsin-Chin Jiang, Industrial Technology Research Institute

pp. 241

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Evening Panel Discussion: IC and Package Co-Design: Challenge or Dream?

IC & Package Co-Design: Challenge or Dream? (Abstract)

Soroush Abbaspour, University of Southern California

Massoud Pedram, University of Southern California

Payam Heydari, University of California, Irvine

pp. 247

PDF

Addressing the IC Designer?s Needs: Integrated Design Software for Faster, More Economical Chip Design (PDF)

Plenary Session II

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pp. 253

Closing the Gap between ASIC and Full Custom: A Path to Quality Design (PDF)

pp. 255

A VLSI System Perspective for Microprocessors Beyond 90nm (PDF)

pp. 257

Session 4A: Power Analysis and Low Power Design

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Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers (Abstract)

Soroush Abbaspour, University of Southern California

Massoud Pedram, University of Southern California

Payam Heydari, University of California, Irvine

pp. 261

PDF

Cycle-accurate Energy Measurement and High-Level Energy Characterization of FPGAs (Abstract)

Hyung Gyu Lee, Seoul National University

Sungyuep Nam, Seoul National University

Naehyuck Chang, Seoul National University

pp. 267

PDF

Quantifying Error in Dynamic Power Estimation of CMOS Circuits (Abstract)

Puneet Gupta, UC San Diego

Andrew B. Kahng, UC San Diego

pp. 273

PDF

MONOLITHIC DC-DC CONVERTER ANALYSIS AND MOSFET GATE VOLTAGE OPTIMIZATION (Abstract)

Volkan Kursun, University of Rochester

Siva G. Narendra, Intel Corporation

Vivek K. De, Intel Corporation

Eby G. Friedman, University of Rochester

pp. 279

PDF

Session 4B: Topics in Device and Interconnect Modeling

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Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design (Abstract)

Dongwoo Lee, University of Michigan

Wesley Kwong, University of Michigan

David Blaauw, University of Michigan

Dennis Sylvester, University of Michigan

pp. 287

PDF

Design and Analysis of Low-Voltage Current-Mode Logic Buffers (Abstract)

Payam Heydari, University of California, Irvine

pp. 293

PDF

Reduced-Order Modeling Based on PRONY?s and SHANK?s Methods via the Bilinear Transformation (Abstract)

Makram M. Mansour, University of Illinois at Urbana-Champaign

Amit Mehrotra, University of Illinois at Urbana-Champaign

pp. 299

PDF

Session 4C: Techniques for High-Speed Circuits and Module Generation

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A Novel Clocking Strategy for Dynamic Circuits (Abstract)

Young Jun Lee, Northeastern University

Jong-Jin Lim, Northeastern University

Yong-Bin Kim, Northeastern University

pp. 307

PDF

Procedural Analog Design (PAD) Tool (Abstract)

Danica Stefanovic, Swiss Federal Institute of Technology, Electronics Labs; University of Nis

Maher Kayal, Swiss Federal Institute of Technology, Electronics Labs

Marc Pastre, Swiss Federal Institute of Technology, Electronics Labs

Vanco B. Litovski, University of Nis

pp. 313

PDF

Parameterized Macrocells with Accurate Delay Models for Core-Based Designs (Abstract)

Makram M. Mansour, University of Illinois at Urbana-Champaign

Mohammad M. Mansour, University of Illinois at Urbana-Champaign

Amit Mehrotra, University of Illinois at Urbana-Champaign

pp. 319

PDF

Session 5A: Timing and Noise Issues in Physical Design

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Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy (Abstract)

Wai-Ching Douglas Lam, Purdue University

Cheng-Kok Koh, Purdue University

Chung-Wen Albert Tsao, Cadence Design Systems

pp. 327

PDF

Minimizing Inter-Clock Coupling Jitter (Abstract)

Ming-Fu Hsiao, National Taiwan University

Malgorzata Marek-Sadowska, University of California, Santa Barbara

Sao-Jie Chen, National Taiwan University

pp. 333

PDF

A Proposal for Routing-Based Timing-Driven Scan Chain Ordering (Abstract)

Puneet Gupta, UC San Diego

Andrew B. Kahng, UC San Diego

Stefanus Mantik, Cadence Design Systems, Inc.

pp. 339

PDF

Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis (Abstract)

Jae-Seok Yang, Samsung Electronics

Jeong-Yeol Kim, Samsung Electronics

Joon-Ho Choi, Samsung Electronics

Moon-Hyun Yoo, Samsung Electronics

Jeong-Taek Kong, Samsung Electronics

pp. 344

PDF

PDL: A New Physical Synthesis Methodology (Abstract)

Toshiyuki Shibuya, Fujitsu Laboratories LTD.

Rajeev Murgai, Fujitsu Laboratories of America, Inc.

Tadashi Konno, Fujitsu LTD.

Kazuhiro Emi, Fujitsu LSI Technology LTD.

Kaoru Kawamura, Fujitsu Laboratories LTD.

pp. 348

PDF

Session 5B: Reliabililty Analysis

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Statistical Modeling for Circuit Simulation (Abstract)

Colin C. McAndrew, Motorola

pp. 357

PDF

Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits (Abstract)

Ming-Dou Ker, National Chiao-Tung University

Hsin-Chyh Hsu, National Chiao-Tung University

Jeng-Jie Peng, Industrial Technology Research Institute

pp. 363

PDF

Coupled Simulation of Circuit and Piezoelectric Laminates (Abstract)

Cheng-gang Xu, Oregon State University

Terri Fiez, Oregon State University

Kartikeya Mayaram, Oregon State University

pp. 369

PDF

Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling (Abstract)

Won-Seok Lee, SAMSUNG Electronics Co., Ltd

Keun-Ho Lee, SAMSUNG Electronics Co., Ltd

Jin-Kyu Park, SAMSUNG Electronics Co., Ltd

Tae-Kyung Kim, SAMSUNG Electronics Co., Ltd

Young-Kwan Park, SAMSUNG Electronics Co., Ltd

Jeong-Taek Kong, SAMSUNG Electronics Co., Ltd

pp. 373

PDF

Static Electromigration Analysis for Signal Interconnects (Abstract)

Chanhee Oh, Motorola, Inc

David Blaauw, University of Michigan

Murat Becer, Motorola, Inc

Vladimir Zolotov, Motorola, Inc

Rajendran Panda, Motorola, Inc

Aurobindo Dasgupta, Intel

pp. 377

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Session 5C: Panel Discussion: Hidden Quality, Crouching Customer-How Much Does the Quality of EDA Tools Impact Electronic Design?

Hidden Quality, Crouching Customer - How Much Does the Quality of EDA Tools Impact Electronic Design? (Abstract)

pp. 383

PDF

Session 6A: Interconnect Parasitic Effects

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On-Chip Interconnect Inductance - Friend or Foe (Invited) (Abstract)

S. Simon Wong, Stanford University

Patrick Yue, Stanford University

Richard Chang, Stanford University

So-Young Kim, Stanford University

Bendik Kleveland, Stanford University

Frank O?Mahony, Stanford University

pp. 389

PDF

Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay (Abstract)

Takashi Sato, Hitachi, Ltd. and Kyoto University

Hiroo Masuda, Semiconductor Technology Academic Research Center

pp. 395

PDF

On the Accuracy of Return Path Assumption for Loop Inductance Extraction for 0.1?m Technology and Beyond (Abstract)

SoYoung Kim, Stanford University

Yehia Massoud, Synopsys Inc.

S. Simon Wong, Stanford University

pp. 401

PDF

Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow (Abstract)

Payman Zarkesh-Ha, LSI Logic Corporation

S. Lakshminarayann, LSI Logic Corporation

Ken Doniger, LSI Logic Corporation

William Loh, LSI Logic Corporation

Peter Wright, LSI Logic Corporation

pp. 405

PDF

Analyzing Internal-Switching Induced Simultaneous Switching Noise (Abstract)

Li Yang, University of Central Florida

J. S. Yuan, University of Central Florida

pp. 410

PDF

Session 6B: Design and Measurement Issues in Testing

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Generation of Hazard Identification Functions (Abstract)

Maria K. Michael, University of Notre Dame

Spyros Tragoudas, Southern Illinois University

pp. 419

PDF

Concurrent Fault Detection in Random Combinational Logic (Abstract)

Petros Drineas, Yale University

Yiorgos Makris, Yale University

pp. 425

PDF

Automatic Repositioning Technique for Digital Cell Based Window Comparators and Implementation within Mixed-Signal DfT Schemes (Abstract)

D. De Venuto, DEE- Politecnico di Bari

M. J. Ohletz, AMI Semiconductor, Belgium

B. Riccò, DEIS Universit? di Bologna

pp. 431

PDF

On Structural vs. Functional Testing for Delay Faults (Abstract)

Angela Krstic, University of California, Santa Barbara

Jing-Jia Liou, National Tsing Hua University

Kwang-Ting (Tim) Cheng, University of California, Santa Barbara

Li-C. Wang, University of California, Santa Barbara

pp. 438

PDF

An Embedded I_DDQ Testing Architecture and Technique (Abstract)

Y. Tsiatouhas, University of Ioannina

Th. Haniotakis, Southern Illinois Univ.

A. Arapoyanni, University of Athens

pp. 442

PDF

Author's Index (PDF)

pp. 447

Participating Organizations (PDF)

pp. 449

Corporate and Media Sponsors (PDF)

pp. 451

Best Paper Award (PDF)

pp. 453

ISQED 2004 Call for Papers (PDF)

pp. 455