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Fourth International Symposium on Quality Electronic Design
An Embedded IDDQ Testing Architecture and Technique
San Jose, California
March 24-March 26
ISBN: 0-7695-1881-8
ASCII Text
x 
 
Y. Tsiatouhas, Th. Haniotakis, A. Arapoyanni, "An Embedded I<sub>DDQ</sub> Testing Architecture and Technique," Quality Electronic Design, International Symposium on, pp. 442, Fourth International Symposium on Quality Electronic Design, 2003.
 
 
BibTex
x
 
@article{ 10.1109/ISQED.2003.1194773,
author = {Y. Tsiatouhas and Th. Haniotakis and A. Arapoyanni},
title = {An Embedded I<sub>DDQ</sub> Testing Architecture and Technique},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2003},
isbn = {0-7695-1881-8},
pages = {442},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2003.1194773},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - An Embedded I<sub>DDQ</sub> Testing Architecture and Technique
SN - 0-7695-1881-8
SP
EP
A1 - Y. Tsiatouhas,
A1 - Th. Haniotakis,
A1 - A. Arapoyanni,
PY - 2003
KW - I<sub>DDQ</sub> Testing
KW - Design for Testability (DFT)
KW - Boundary Scan
KW - IEEE 1149.1
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
Y. Tsiatouhas, University of Ioannina
Th. Haniotakis, Southern Illinois Univ.
A. Arapoyanni, University of Athens
In this paper an embedded IDDQ testing architecture is presented that targets to overcome the excessive hardware overhead requirements in built-in current sensing based testing applications. Moreover, a technique that utilises the IEEE 1149.1 boundary scan standard to control the proposed architecture is provided. The proposed solution is characterised by low silicon area requirements and permits the application of IDDQ testing also in case that the chip is mounted on a printed circuit board.
Index Terms:
I<sub>DDQ</sub> Testing, Design for Testability (DFT), Boundary Scan, IEEE 1149.1
Citation:
Y. Tsiatouhas, Th. Haniotakis, A. Arapoyanni, "An Embedded IDDQ Testing Architecture and Technique," isqed, pp.442, Fourth International Symposium on Quality Electronic Design, 2003
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