Fourth International Symposium on Quality Electronic Design Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling San Jose, California March 24-March 26 ISBN: 0-7695-1881-8
In this paper, the influence of floating dummy metal-fills on interconnect parasitic is analyzed with the variations of possible factors which can affect the capacitance. Recently proposed chip-level metal-fill modeling, replacing metal-fill layer with effective high-k dielectric, has been reviewed in detail. Using a systematized modeling flow, the property of the effective permittivity in the modeled geometry is examined. Validation with the realistic 3D structures clearly demonstrates the importance and correctness of the geometry modeling.
Citation:
Won-Seok Lee, Keun-Ho Lee, Jin-Kyu Park, Tae-Kyung Kim, Young-Kwan Park, Jeong-Taek Kong, "Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling," isqed, pp.373, Fourth International Symposium on Quality Electronic Design, 2003 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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