loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Fourth International Symposium on Quality Electronic Design
PDL: A New Physical Synthesis Methodology
San Jose, California
March 24-March 26
ISBN: 0-7695-1881-8
Toshiyuki Shibuya, Fujitsu Laboratories LTD.
Rajeev Murgai, Fujitsu Laboratories of America, Inc.
Tadashi Konno, Fujitsu LTD.
Kazuhiro Emi, Fujitsu LSI Technology LTD.
Kaoru Kawamura, Fujitsu Laboratories LTD.
In this paper, we propose a new physical synthesis methodology, PDL, which relaxes the timing constraints to obtain best optimality in terms of layout quality and timing quality. It provides a common database for delay calculation, logic optimization, placement, and routing tools so that they can work and interact closely. We present results on industrial circuits showing the efficacy of this methodology.
Citation:
Toshiyuki Shibuya, Rajeev Murgai, Tadashi Konno, Kazuhiro Emi, Kaoru Kawamura, "PDL: A New Physical Synthesis Methodology," isqed, pp.348, Fourth International Symposium on Quality Electronic Design, 2003
Usage of this product signifies your acceptance of the Terms of Use.