Simultaneous switching events in the clock lines and almost simultaneous switching events of sequential and combinational logic elements cause large L?di/dt and IR voltage variations in the power and ground network of a circuit. This is known as power supply noise and it affects the performance and reliability of the entire circuit. In this paper, we propose a genetic algorithm based clock scheduling approach for minimizing the number of simultaneous switching events such that the power supply noise is suppressed. We ensure that in any generation of the genetic algorithm process, there will be feasible clock schedules present in the gene pool by the use of gene therapy. Experimental results on benchmark circuits show an average reduction of 26.2% in the peak current, an average reduction of 37.9% in the current swing, and an average reduction of 46.2% in voltage variations in the power lines.