Fourth International Symposium on Quality Electronic Design A Novel Clocking Strategy for Dynamic Circuits San Jose, California March 24-March 26 ISBN: 0-7695-1881-8
This paper proposes a new clocking strategy for dynamic circuit. It provides faster performance and smaller area than conventional clocking scheme. The proposed clocking scheme for dynamic circuits provides the solution of the problem caused by logic polarity and clock skew problem simultaneously. To demonstrate the proposed clocking strategy, a 32 bit Carry Look Ahead adder (CLA) is designed and simulated using 0.25um CMOS technology to demonstrate 32.7% faster speed than the conventional clocking scheme and 19.4% transistor counter reduction.
Citation:
Young Jun Lee, Jong-Jin Lim, Yong-Bin Kim, "A Novel Clocking Strategy for Dynamic Circuits," isqed, pp.307, Fourth International Symposium on Quality Electronic Design, 2003 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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