Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits

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Fourth International Symposium on Quality Electronic Design

San Jose, California

March 24-March 26

ISBN: 0-7695-1881-8

	ASCII Text	x
	C. T. Chuang, R. V. Joshi, R. Puri, K. Kim, "Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits," Quality Electronic Design, International Symposium on, pp. 153, Fourth International Symposium on Quality Electronic Design, 2003.

	BibTex	x
	@article{ 10.1109/ISQED.2003.1194724, author = {C. T. Chuang and R. V. Joshi and R. Puri and K. Kim}, title = {Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2003}, isbn = {0-7695-1881-8}, pages = {153}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2003.1194724}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits SN - 0-7695-1881-8 SP EP A1 - C. T. Chuang, A1 - R. V. Joshi, A1 - R. Puri, A1 - K. Kim, PY - 2003 KW - null VL - 0 JA - Quality Electronic Design, International Symposium on ER -

C. T. Chuang, IBM T. J. Watson Research Center

R. V. Joshi, IBM T. J. Watson Research Center

R. Puri, IBM T. J. Watson Research Center

K. Kim, IBM T. J. Watson Research Center

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2003.1194724

This paper reviews the circuit design considerations of scaled sub-0.1 ?m partially-depleted SOI (PD/SOI) CMOS circuits for high-performance digital applications. The impact of technology/device scaling and design challenges are highlighted. Unique design aspects and issues resulting from the scaling of PD/SOI device structure, such as parasitic bipolar effect and reduced-V_T leakage, hysteretic V_T variation, low-voltage impact ionization, higher V_T,lin to maintain adequate V_T,sat; scaling/ thinning of Si film, gate-to-body tunneling current, self-heating, soft error rate (SER), and the introduction of strained-Si channel on SOI are addressed.

Citation:

C. T. Chuang, R. V. Joshi, R. Puri, K. Kim, "Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits," isqed, pp.153, Fourth International Symposium on Quality Electronic Design, 2003

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