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International Symposium on Quality Electronic Design (ISQED '01)
Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1
San Jose, California
March 26-March 28
ISBN: 0-7695-1025-6
ASCII Text
x 
 
K. Tatas, A. Argyriou, M. Dasigenis, D. Soudris, N. Zervas, "Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1," Quality Electronic Design, International Symposium on, pp. 456, International Symposium on Quality Electronic Design (ISQED '01), 2001.
 
 
BibTex
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@article{ 10.1109/ISQED.2001.915271,
author = {K. Tatas and A. Argyriou and M. Dasigenis and D. Soudris and N. Zervas},
title = {Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2001},
isbn = {0-7695-1025-6},
pages = {456},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2001.915271},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1
SN - 0-7695-1025-6
SP
EP
A1 - K. Tatas,
A1 - A. Argyriou,
A1 - M. Dasigenis,
A1 - D. Soudris,
A1 - N. Zervas,
PY - 2001
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
K. Tatas, Democritus University of Thrace
A. Argyriou, Democritus University of Thrace
M. Dasigenis, Democritus University of Thrace
D. Soudris, Democritus University of Thrace
N. Zervas, University of Patras
Data Memory hierarchy optimization and partitioning for a widely used multimedia application kernel known as the hierarchical motion estimation algorithm is undertaken, with the use of global loop and data-reuse transformations for three different embedded processor architecture models. Exhaustive exploration of the obtained results clarifies the effect of the transformations on power, area, and performance and also indicates a relation between the complexity of the application and the power savings obtained by this strategy. Furthermore, the significant contribution of the instruction memory, even after the application of performance optimizations to the total power budget becomes evident and a methodology is introduced in order to reduce this component.
Citation:
K. Tatas, A. Argyriou, M. Dasigenis, D. Soudris, N. Zervas, "Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1," isqed, pp.456, International Symposium on Quality Electronic Design (ISQED '01), 2001
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