The wide range and rapid increase in the complexity of CAD tools demand proven and safe design flows. This paper presents a fully validated methodology integrated as analog design flow to design non volatile memories. Specifically, it has been applied to designs in 0.35um EEPROM and 0.13um Flash Memory processes developed in our company. The remarkable feature of the proposed methodology is the excellent integration between CAD tools released by different vendors and internally developed solutions. Furthermore, we show a flow which provides full compatibility and flexibility among analog design steps that could cut down time-to-design, time-to-market and streamline the design quality, thus enhancing the circuit yield and robustness.