Functional decomposition seems to be the most effective circuit synthesis approach for look-up table (LUT) FPGAs, (C)PLDs and complex gates. Since LUT FPGAs are used in numerous important applications and constitute a foundation for the novel re-configurable system-on-a-chip platforms, an adequate synthesis for this target is of primary importance for the modern system industry. In the functional decomposition targeting LUT FPGAs, the circuit is constructed by recursively decomposing a given function and its sub-functions until each of the resulting sub-functions can be directly implemented with a LUT. The input support selection for the sub-functions that are constructed in this process decides the quality of the resulting multi-level circuit to a high degree. In this paper, we propose a new effective method for the sub-function input support selection and discuss its application in our circuit synthesis tool that targets LUT-based FPGAs. The experimental results demonstrate that the proposed approach leads to extremely fast and very small circuits. The circuits consume on average over 2 times less logic blocks (CLBs) and are over 1.5 times faster than the circuits produced by the best state-of-the-art commercial tools.