The ELITE (Essential Library in Technology Evolution) design methodology of foundation IP (Intellectual Property) for synthesis quality is presented in this paper. The design idea is derived from RISC (Reduced Instruction Set Computer) design philosophy in computer architecture. After analyzing the use rate of each cell with benchmarks, it shows that too many cells in a library not only increase the loading on library development and maintenance but also affect the quality of the logic synthesis. The ELITE design methodology proposes removing unused and rarely used cells from original library, then composing the most frequently used cells by logic synthesis tool to a new ELITE library. Due to fewer cells in a library, designers can significantly reduce the development time of cell library, shorten design time and pay more attention to improve the quality of the cell library with deep sub-micron process characteristics. Moreover, the experimental results show that, when ELITE libraries are used in logic synthesis the speed measurements improve 14.22% to 17.35% and the area measurements decrease 13.98% to 15.5% in unconstraint condition. The experiments of ELITE library has almost equal synthesis results when it is compared to conventional library with aggressive constraints. However, there are only 34 cells in ELITE library compared with 470 ones in the original library.