Effective Built-In Self-Test (BIST) schemes using deterministic sequences generated by small counters have been proposed in the past for the common multiplier/accumulator pair. In this paper we show how near complete testability can be achieved with a regular counter-generated deterministic test set for the shifter-accumulator pair (accumulation performed either by an adder or an ALU) which appears very often in embedded processor or DSP datapaths. The BIST scheme provides near complete coverage with respect to the stuck-at fault model for any datapath width as it is verified by a comprehensive set of experiments. The proposed BIST scheme uses the same Test Pattern Generation (counters) and Output Data Evaluation (accumulators) resources as in our earlier BIST schemes for multiplier/accumulator pairs, thus completing a deterministic counter-based datapath BIST architecture.