This paper presents a novel power grid modeling technique that can be used in hierarchical power network analysis of multi-million gate designs. The RC network of the power grid of a macro block is extracted and reduced by an AWE-based algorithm. The resulting model replaces the macro blocks during the top level power network analysis, thus greatly reduces both memory and CPU time usage. Our experiments show that more than 90% of R's and C's in the original power network can be reduced with less than 10% loss in accuracy. Furthermore, the CPU time required for the power network analysis of full-chip designs is reduced by 10 to 100 times.