Performance of high-speed VLSI circuits is increasingly limited by interconnect coupling noise. We present simple and improved analytical models for noise phenomena due to coupling capacitance. We extend the P model presented in [4] to accommodate a segmented aggressor. We also include a linear driver resistance in the modeling of both victims and aggressors to measure their estimate on peak noise. Finally, we extend this model to multiple segmented aggressors by superposing noise contributions of individual aggressors and sweeping the result in the time domain to determine peak noise (in contrast to adding the individual peak noise values for individual aggressors). Accuracy in the results depends greatly on actual positioning of victim-aggressor overlaps. We find that previous models that assume aggressors run parallel to the victim net for its entire length do not yield peak noise results nearly as close to SPICE-computed values. We also find that inclusion of driver resistance in the model improves accuracy. Our noise model for a single segmented aggressor is within ~ 16% of SPICE. Results for two segmented aggressors are within acceptable tolerances with respect to SPICE, but error increases with the number of aggressors. We note that these results are almost always pessimistic.